Semiconductor device having symmetric conductive interconnection patterns

ABSTRACT

A semiconductor device may include a lower interlayer dielectric layer, a conductive interconnection pattern structure and a filling pattern over the lower interlayer dielectric layer, and a top interlayer dielectric layer over the conductive interconnection pattern structure and the filling patterns. Each of the conductive interconnection pattern structure may include an intermediate pattern in the center thereof, a first conductive interconnection pattern on a first side surface of the intermediate pattern, and a second conductive interconnection pattern on a second side surface of the intermediate pattern. The first conductive interconnection pattern and the second conductive interconnection pattern may have a symmetrical structure to each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

The patent document claims priority under 35 U.S.C. § 119 of KoreanPatent Application No. 10-2018-0085972, filed on Jul. 24, 2018, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

The technology and implementations disclosed in this patent documentrelate to symmetric conductive interconnection patterns having smallerwidths and/or spaces than widths and/or spaces of mask patterns formedin a photolithography process, and a method of forming the same.

BACKGROUND

As the degree of integration of a semiconductor device increases, thehorizontal widths and intervals of conductive interconnection patternsgradually become smaller. In order to form fine patterns, expensivephotolithography facilities and complicated photolithography processesare used. For example, a double exposure process, a double patterningprocess, a double spacer process or the like is used. These doubleprocesses are very complex and have a high probability of failurebecause similar processes are performed twice.

SUMMARY

Exemplary embodiments provide a method of forming conductiveinterconnection patterns having finer widths and spaces than line widthsand intervals of mask patterns formed in a photolithography process.

Exemplary embodiments provide a method of forming conductiveinterconnection patterns having finer widths and spaces than a linewidth and an interval of a pattern primarily formed by using a singlespacer forming technique.

Various objects in specific implementations of the disclosed technologymay be achieved and the applications of the disclosed technology are notlimited to the specific implementations or examples disclosed in thispatent document.

In accordance with an embodiment, a semiconductor device may include alower interlayer dielectric layer; conductive interconnection patternstructure and filling pattern over the lower interlayer dielectriclayer; and an upper interlayer dielectric layer over the conductiveinterconnection pattern structure and the filling pattern. Each of theconductive interconnection pattern structure may include an intermediatepattern in the center thereof; a first conductive interconnectionpattern on a first side surface of the intermediate pattern; and asecond conductive interconnection pattern on a second side surface ofthe intermediate pattern. The first conductive interconnection patternand the second conductive interconnection pattern may have a symmetricalstructure to each other.

In accordance with an embodiment, a method for fabricating asemiconductor device may include forming a stopper layer; forming anintermediate pattern material layer over the stopper layer; forming aplurality of first preliminary intermediate patterns by patterning theintermediate pattern material layer; forming a plurality of secondpreliminary intermediate patterns by shrinking the first preliminaryintermediate patterns; forming a conductive material layer to cover thesecond preliminary intermediate patterns; forming a plurality ofpreliminary conductive interconnection patterns by patterning theconductive material layer; forming a filling layer between thepreliminary conductive interconnection patterns; and forming a pluralityof intermediate patterns, a plurality of conductive interconnectionpatterns and a plurality of filling patterns by removing top portions ofthe filling layer, the preliminary conductive interconnection patternsand the second preliminary intermediate patterns.

In accordance with an embodiment, a method for fabricating asemiconductor device may include forming a lower interlayer dielectriclayer over a substrate; forming a stopper layer over the lowerinterlayer dielectric layer; forming first preliminary intermediatepatterns over the stopper layer; forming second preliminary intermediatepatterns by shrinking the first preliminary intermediate patterns;forming preliminary conductive interconnection patterns to cover topsurfaces and both side surfaces of the second preliminary intermediatepatterns; forming a filling layer between the preliminary conductiveinterconnection patterns; forming intermediate patterns with sidesurfaces, conductive interconnection patterns on side surfaces of theintermediate patterns and filling patterns between the conductiveinterconnection patterns by removing a top portion of each of thefilling layer, the preliminary conductive interconnection patterns andthe second preliminary intermediate patterns; forming a capping layerover the intermediate patterns, the conductive interconnection patternsand the filling patterns; and forming an upper interlayer dielectriclayer over the capping layer.

The details of other embodiments are included in the detaileddescription and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 9 are cross-sectional views illustrating a method of formingconductive interconnection patterns of a semiconductor memory device inaccordance with an embodiment of the disclosure.

FIGS. 10 to 15 are cross-sectional views illustrating a method offorming conductive interconnection patterns of a semiconductor memorydevice in accordance with an embodiment of the disclosure.

DETAILED DESCRIPTION

Various embodiments will be described below in more detail withreference to the accompanying drawings. Embodiments of the presentdisclosure may, however, have different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the claims to those skilledin the art.

Throughout the specification, like reference numerals refer to the sameelements. Therefore, although the same or similar reference numerals arenot mentioned or described in the corresponding drawing, the referencenumerals may be described with reference to other drawings. Furthermore,although elements are not represented by reference numerals, theelements may be described with reference to other drawings.

FIGS. 1 to 9 are cross-sectional views illustrating a method of formingconductive interconnection patterns of a semiconductor device inaccordance with an embodiment.

Referring to FIG. 1, a method of forming the conductive interconnectionpatterns of a semiconductor device may include forming a lowerinterlayer dielectric layer 20 on a substrate 10 by performing a firstdeposition process; forming a stopper layer 30 on the lower interlayerdielectric layer 20 by performing a second deposition process; formingan intermediate pattern material layer 40 on the stopper layer 30 byperforming a third deposition process; and forming mask patterns M onthe intermediate pattern material layer 40 by performing aphotolithography process.

The substrate 10 may include at least one of a mono-crystalline siliconwafer, an epitaxially grown mono-crystalline silicon layer, or aSilicon-On-Insulator (SOI) layer. In some embodiments, the substrate 10may be a dielectric material covering various electrical circuits.

The lower interlayer dielectric layer 20 may include a dielectricmaterial covering various electrical circuits (not illustrated) formedon the substrate 10. For example, the lower interlayer dielectric layer20 may include at least one of silicon oxide (SiO₂); silicon nitride(SiN); silicon oxynitride (SiON); silicon hydride oxide (SiOH); orsilicon carbide oxide (SiCO), or any combination thereof. The firstdeposition process may include a chemical vapor deposition (CVD)process.

The stopper layer 30 may include a dielectric material, denser andharder than both the lower interlayer dielectric layer 20 and theintermediate pattern material layer 40. The stopper layer 30 may includea material different from, or not included in, the lower interlayerdielectric layer 20, so that stopper layer 30 has a different etchselectivity from both the lower interlayer dielectric layer 20 and theintermediate pattern material layer 40. For example, the stopper layer30 may include at least one of silicon nitride (SiN); silicon oxynitride(SiON); hydrogen (H)-containing material such as silicon hydride oxide(SiOH); carbon (C)-containing material such as silicon carbide oxide(SiCO); silicon carbide nitride (SiCN); or silicon carbide oxynitride(SiCON), or any combination thereof. Thus, the second deposition processmay include a CVD process to form a silicon nitride layer.

The intermediate pattern material layer 40 may include at least one ofsilicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride (SiON),hydrogen (H)-containing material such as silicon hydride oxide (SiOH),carbon (C)-containing material such as silicon carbide oxide (SiCO),silicon carbide nitride (SiCN), or silicon carbide oxynitride (SiCON),or any combination thereof. For example, the third deposition processmay include a CVD process to form a silicon oxide layer.

The mask patterns M may include organic patterns containing an organicpolymeric material such as photoresist, and/or other inorganic patternssuch as silicon oxide (SiO₂), silicon nitride (SiN), silicon oxynitride(SiON), silicon carbide nitride (SiCN), or silicon carbide oxynitride(SiCON).

Horizontal widths W1 of the mask patterns M may be substantially equalor similar to horizontal intervals W2 between the mask patterns M. Thehorizontal widths W1 of the mask patterns M and the horizontal intervalsW2 between the mask patterns M may be dimensions that are at or close tothe minimum resolution of photolithography processes. The minimumresolution may represent or refer to the minimum widths and/or minimumintervals within patterns that may be formed in any givenphotolithography apparatus.

Referring to FIG. 2, the method may include patterning the intermediatepattern material layer 40 by performing a first etch process using themask patterns M as etch masks. The intermediate pattern material layer40 may be patterned into first preliminary intermediate patterns 41.Each of the first preliminary intermediate patterns 41 may have a lineor bar-like shape extending horizontally. First trench spaces TS1 may bepresent between the first preliminary intermediate patterns 41. Thestopper layer 30 may be exposed between the first preliminaryintermediate patterns 41. In the first etch process, vertical heightsand horizontal widths, illustrated in FIG. 2, of the mask patterns M maybe reduced.

Referring to FIG. 3, the method may include removing the mask patterns Mby performing an ashing process or a stripping process, for example. Theashing process may include an oxygen (O₂) plasma process. The strippingprocess may include a sulfuric acid boiling process and a wet removingprocess using hydrofluoric acid or phosphoric acid. First horizontalwidths Wp1 of the first preliminary intermediate patterns 41 may besubstantially equal or similar to first horizontal widths Ws1 of thefirst trench spaces TS1, namely, Wp1=Ws1. Referring back to FIG. 1, thefirst horizontal widths Wp1 of the first preliminary intermediatepatterns 41 may be substantially equal or similar to or smaller than thehorizontal widths W1 of the mask patterns M. The first horizontal widthsWs1 of the first trench spaces TS1 may be substantially equal or similarto or greater than the horizontal intervals W2 between the mask patternsM.

Referring to FIG. 4, the method may include forming second preliminaryintermediate patterns 42 by shrinking the first preliminary intermediatepatterns 41 by performing a shrinking process. The shrinking process mayinclude a soft etch process using a diluted etchant or a strong cleaningprocess using concentrated cleaning fluid. For example, the forming ofthe second preliminary intermediate patterns 42 may include partiallyremoving the upper and all side portions or parts of the firstpreliminary intermediate patterns 41 by performing an isotropic etchprocess or the like. The first preliminary intermediate patterns 41 arereduced in size to the second preliminary intermediate patterns 42. Thefirst trench spaces TS1 may be transformed into widened second trenchspaces TS2 as material is removed from side areas or regions of firstpreliminary intermediate patterns 41. That is, the shrinking process mayinclude widening the first trench spaces TS1 to form the second trenchspaces TS2. Horizontal widths Ws2 of the second trench spaces TS2 may beapproximately three times greater than horizontal widths Wp2 of thesecond preliminary intermediate patterns 42. The ratio of the dimensionsof horizontal widths Wp2 to horizontal widths Ws2 may be 3:1. Verticalheights, i.e., thicknesses may shrink in a half proportion of the firstpreliminary intermediate patterns 41.

Referring to FIG. 5, the method may further include entirely forming aconductive material layer 60 to cover the exposed surfaces of secondpreliminary intermediate patterns 42 by performing a deposition process.This may be the fourth deposition process in the method. For example,the conductive material layer 60 may include a conductor such as ametal. The conductive material layer 60 may completely cover the secondpreliminary intermediate patterns 42. The conductive material layer 60may be formed on, for example in a semi-conformal manner, along theprofiles of the second preliminary intermediate patterns 42. Thedeposition process may include a sputtering process, a Physical VaporDeposition (PVD) process or a CVD process to form a metal layer.

Referring to FIG. 6, the method may further include forming firstpreliminary conductive interconnection patterns 61 by blanket-etchingthe conductive material layer 60 in a second etch process. The secondetch process may include an anisotropic etch-back process. For example,the second etch process may include a physical sputtering etch process.As the conductive material layer 60 shrinks or is reduced in bothvertical and horizontal directions, the first preliminary conductiveinterconnection patterns 61 may be formed in a mound or sheath-likeshapes covering or surrounding the second preliminary intermediatepatterns 42 using the etch-back process to form a spacer shape. In otherwords, the first preliminary conductive interconnection patterns 61 maycompletely cover the top and side surfaces of the second preliminaryintermediate patterns 42. The surface of the stopper layer 30 may beexposed between the first preliminary conductive interconnectionpatterns 61. The first preliminary conductive interconnection patterns61 may be converted into or configured for use as individual patternsthat are physically and electrically separated from one another.

Referring to FIG. 7, the method may further include wholly or entirelyforming a filling layer 70 covering the first preliminary conductiveinterconnection patterns 61 by performing a deposition process. This maybe a fifth deposition process. The filling layer 70 may fill spacesbetween the first preliminary conductive interconnection patterns 61.The filling layer 70 may include at least one of silicon oxide (SiO₂);silicon nitride (SiN); or silicon oxynitride (SiON), or any combinationthereof. The deposition process may include a CVD process to form asilicon oxide layer.

Referring to FIG. 8, the method may further include forming conductivepattern structures 100A and filling patterns 71 by partially removingupper portions or regions of the filling layer 70; the first preliminaryconductive interconnection patterns 61; and the second preliminaryintermediate patterns 42 by performing a Chemical Mechanical Polishing(CMP) process. Each resulting conductive pattern structure 100A mayinclude intermediate patterns 43 between or sandwiched by conductiveinterconnection patterns 62L and 62R. For example, the conductivepattern structure 100A includes an intermediate pattern 43 positioned inthe center, left conductive interconnection patterns 62L positioned onthe left side of the intermediate pattern 43, and right conductiveinterconnection pattern 62R positioned on the right side of theintermediate pattern 43. Two or more conductive pattern structures 100Amay be formed spaced apart on stopper layer 30. The filling patterns 71may be formed between the conductive pattern structures 100A and onstopper layer 30. For example, the left conductive interconnectionpatterns 62L may be formed on left side surfaces of the intermediatepatterns 43, and right conductive interconnection patterns 62R may beformed on the right side surfaces of the intermediate patterns 43. Eachof the left conductive interconnection patterns 62L may have a rightside surface, closer to in contact with the intermediate pattern 43,that is substantially vertical and flat, and a left side surface that isnon-planar and tapered in a vertical direction, from a wider base (widerlower portion) closer to or in contact with the surface of the stopperlayer 30 to a narrower upper portion. For example, a cross-section ofthe left side surface of the conductive interconnection pattern 62L maybe rounded and inclined, for example by following a circular orelliptical arc, so that the upper portion is narrower, and the lowerportion is wider. Each of the right conductive interconnection patterns62R may have a left side surface, closer to or in contact with theintermediate pattern 43, that is substantially vertical and flat, and aright side surface that is non-planar and tapered in a verticaldirection, from a wider base (wider lower portion) closer to or incontact with the surface of the stopper layer 30 to a narrower upperportion. For example, a cross-section of the right side surface of theconductive interconnection pattern 62R may be rounded and inclined sothat the upper portion is narrower, and the lower portion is wider, forexample along a circular or elliptical arc. The left conductiveinterconnection patterns 62L and the right conductive interconnectionpatterns 62R may form a bilaterally symmetrical structure with anintermediate pattern 43 at the center of the structure. For example, theleft conductive interconnection patterns 62L and the right conductiveinterconnection patterns 62R may be alternately disposed on either sideof, to face or opposite to each other, an intermediate pattern 43. Theleft conductive interconnection patterns 62L and the right conductiveinterconnection patterns 62R may have substantially flat or planarbottom, or lower, surfaces and top, or upper, surfaces. The horizontalwidths of the top surfaces of the left conductive interconnectionpatterns 62L and the right conductive interconnection patterns 62R maybe smaller than Wa, the horizontal widths of the bottom surfaces, closerto or in contact with the stopper layer 30, of the left conductiveinterconnection patterns 62L and the right conductive interconnectionpatterns 62R. The filling pattern 71 may be disposed between theconductive pattern structures 100A. For example, the filling pattern 71can be formed on the stopper layer 30 in spaces or gaps between the leftconductive patterns 62L of one conductive pattern structure 100A and theright conductive pattern 62R of an adjacent conductive pattern structure100A. The filling pattern 71 may also be disposed between the rightconductive pattern 62R of one conductive pattern structure 100A and theleft conductive pattern 62L of another adjacent conductive patternstructure 100A.

Each of the intermediate patterns 43 may have both side surfaces thatare substantially vertical and flat closer to or in contact with theleft conductive interconnection patterns 62L and the right conductiveinterconnection patterns 62R. Each of the filling patterns 71 may haveside surfaces that are non-planar and tapered in a vertical direction,from a narrower base (narrower lower portion) closer to or in contactwith the stopper layer 30 to a wider upper surface. For example, bothside surfaces of the filling pattern 71 may be negatively rounded sothat the upper portion is wider and the lower portion is narrower. Therounded sides may have a cross-section shape that follows a circular oran elliptical arc.

The CMP process may include a first CMP process, a second CMP process,and a third CMP process. The first CMP process may mainly remove thefilling layer 70. The second CMP process may remove the filling layer 70and the preliminary conductive interconnection patterns 61. The thirdCMP process may remove the filling layer 70, the preliminary conductiveinterconnection patterns 61, and the second preliminary intermediatepatterns 42. The intermediate patterns 43, the conductiveinterconnection patterns 62L and 62R, and the filling patterns 71 may besubstantially coplanar with one another. In the second and third CMPprocesses, the intermediate patterns 43 may be used as a CMP stopperlayer.

In embodiments disclosed herein, the left conductive interconnectionpatterns 62L and the right conductive interconnection patterns 62R mayhave horizontal widths Wa and/or horizontal intervals Wb closer to or incontact with the stopper layer 30 that are smaller than the minimumhorizontal widths W1 and/or the minimum horizontal intervals W2 of thelimit (marginal) resolution of the photolithography process. As anexample, a horizontal interval Wb between a left conductiveinterconnection pattern 62L and a right conductive interconnectionpattern 62R may be equal or similar to the horizontal width of anintermediate pattern 43 and/or a filling pattern 71, each of which areless than W1 and/or W2.

In embodiments disclosed herein, the sum of the horizontal width Wa ofthe left or right conductive interconnection pattern 62L or 62R and thehorizontal interval Wb between the left conductive interconnectionpattern 62L and the right conductive interconnection pattern 62R may beequal or substantially equal to the minimum horizontal width W1 and/orthe minimum horizontal interval W2 of the limit resolution. For example,Wa+Wb=W1=W2=Wp1=Ws1.

Referring to FIG. 9, the method may include forming a capping layer 80on the conductive pattern structures 100A and the filling patterns 71 byperforming a deposition process. This may be the sixth depositionprocess. The method may further include forming an upper interlayerdielectric layer 90 on the capping layer 80 by performing anotherdeposition process, which can be a seventh deposition process. Thecapping layer 80 may include a material denser and harder than thematerial used to form intermediate patterns 43 and the filling patterns71. For example, the capping layer 80 may include at least one ofsilicon nitride (SiN), silicon oxynitride (SiON) or a combinationthereof. Accordingly, the sixth deposition process may include a CVDprocess for depositing silicon nitride (SiN). The upper interlayerdielectric layer 90 may include at least one of silicon oxide (SiO₂);silicon nitride (SiN); silicon oxynitride (SiON); silicon hydride oxide(SiOH); or silicon carbide oxide (SiCO), or any combination thereof. Forexample, the seventh deposition process may include a CVD process toform silicon oxide (SiO₂).

In disclosed embodiments, patterns having finer resolution than thelimit (marginal) resolution may be formed using a mask patterns only ina photolithography process.

FIGS. 10 to 15 are cross-sectional views illustrating a method offorming conductive interconnection patterns of a semiconductor device inaccordance with an embodiment.

Referring to FIG. 10, a method of forming the conductive interconnectionpatterns of a semiconductor device may include sequentially forming alower interlayer dielectric layer 20, a stopper layer 30, anintermediate pattern material layer 40 and mask patterns M over asubstrate 10, forming first preliminary intermediate patterns 41 bypatterning the intermediate pattern material layer 40, removing the maskpatterns M, and forming second preliminary intermediate patterns 42 byshrinking the first preliminary intermediate patterns 41, by performingthe series of processes described above and with reference to FIGS. 1 to4, and forming a barrier material layer 50 to cover or surround exposedareas of the second preliminary intermediate patterns 42 and the exposedportions of stopper layer 30.

The barrier material layer 50 may be conformally formed on the top andside surfaces of the second preliminary intermediate patterns 42 and theexposed surfaces of the stopper layer 30. The barrier material layer 50may include at least one of conductive barrier materials such astitanium nitride (TiN); tantalum nitride (TaN); or tungsten nitride(WN), or dielectric barrier materials such as silicon nitride (SiN) orsilicon oxynitride (SiON). The barrier material layer 50 may be formedby performing a PVD process or a CVD process.

Referring to FIG. 11, the method may further include forming aconductive material layer 60 wholly or entirely covering the exposedsurface of barrier material layer 50 by performing the process describedabove and with reference to FIG. 5. The barrier material layer 50 mayenhance the adhesion between the second preliminary intermediatepatterns 42 and the conductive material layer 60.

Referring to FIG. 12, the method may further include forming preliminaryconductive interconnection patterns 61 by blanket-etching the conductivematerial layer 60 by performing the process described above and withreference to FIG. 6, and forming preliminary barrier patterns 51 bysequentially etching the barrier material layer 50 to create gaps orspaces in the conductive material layer 60 and the barrier materiallayer 50 closer to or in contact with the stopper layer 30. As a result,portions of the upper surface of the stopper layer 30 may be exposedbetween the preliminary conductive interconnection patterns 61 and thepreliminary barrier patterns 51.

Referring to FIG. 13, the method may further include forming a fillinglayer 70 across the resultant structure by performing the processdescribed above and with reference to FIG. 7.

Referring to FIG. 14, the method may further include forming aconductive pattern structure 100B and filling patterns 71 by partiallyremoving upper regions of the filling layer 70, the preliminaryconductive interconnection patterns 61, the preliminary barrier patterns51, and the second preliminary intermediate patterns 42 by performingCMP processes. The conductive pattern structure 100B may include anintermediate pattern 43, a left barrier pattern 52L, a right barrierpattern 52R, a left conductive interconnection pattern 62L, and a rightconductive interconnection pattern 62R. The filling patterns 71 may bedisposed between the conductive pattern structures 100B.

Each of the intermediate patterns 43 may have both side surfaces thatare substantially vertical and flat closer to or in contact with theleft conductive interconnection patterns 62L and the right conductiveinterconnection patterns 62R. Each of the filling patterns 71 may haveboth side surfaces that are non-planar and tapered in a verticaldirection, from a narrower base closer to or in contact with the stopperlayer 30 to a wider upper surface. For example, both side surfaces ofthe filling pattern 71 may be rounded negatively so that the upperportion is wider, and the lower portion is narrower. The rounded sidesmay have a cross-section shape that that follows a circular or anelliptical arc.

Each of the left barrier patterns 52L may include a vertical portionbetween the left side surface of an intermediate pattern 43 and theright side surface of a left conductive interconnection pattern 62L, anda horizontal portion between the bottom, or lower, surface of the leftconductive interconnection pattern 62L and the top surface of thestopper layer 30. Each of the right barrier patterns 52R may include avertical portion between the right side surface of an intermediatepattern 43 and the left side surface of a right conductiveinterconnection pattern 62R, and a horizontal portion between the bottomsurface of the right conductive interconnection pattern 62R and the topsurface of the stopper layer 30. In other words, each of the leftbarrier patterns 52L may have an inverted-L shaped cross-section, andeach of the right barrier patterns 52R may have an L-shapedcross-section. Accordingly, the left barrier patterns 52L and the rightbarrier patterns 52R may form a bilaterally symmetrical structurecentered on an intermediate pattern 43.

Each of the left conductive interconnection patterns 62L may have aright side surface, closer to or in contact with a left barrier pattern52L, that is substantially vertical and flat and a left side surfacethat is non-planar and tapered in a vertical direction, from a widerbase closer to or in contact with the stopper layer 30 to a narrowerupper portion. For example, a cross-section of the left side surface ofa conductive interconnection pattern 62L may be rounded and inclined,for example by following a circular or elliptical arc, so that the upperportion is narrower and the lower portion is wider. Each of the rightconductive interconnection patterns 62R may have a left side surface,close to or in contact with a right barrier pattern 52R, that issubstantially vertical and flat and a right side surface that isnon-planar and tapered in a vertical direction, from a wider base closerto or in contact with the stopper layer 30 to a narrower upper portion.For example, a cross-section of the right side surface of a conductiveinterconnection pattern 62R may be rounded and inclined so that theupper portion is narrower and the lower portion is wider, for examplealong a circular or elliptical arc. The left conductive interconnectionpatterns 62L and the right conductive interconnection patterns 62R mayform a bilaterally symmetrical structure with an intermediate pattern 43at the center of the structure.

Each of the filling patterns 71 may have tapered side surfaces withnegative slopes. For example, both side surfaces of the filling pattern71 may be rounded negatively so that the upper portion is wider and thelower portion is narrower. The rounded sides may have a cross-sectionshape that that follows a circular or an elliptical arc.

The intermediate patterns 43, the left and right barrier patterns 52Land 52R, the left and right conductive interconnection patterns 62L and62R and the filling patterns 71 may be substantially coplanar with oneanother as a result of a CMP process. The intermediate patterns 43 maybe used as a CMP stopper layer.

Referring to FIG. 15, the method may further include forming a cappinglayer 80 on the conductive pattern structures 100B and forming a topinterlayer dielectric layer 90 on the capping layer 80, by performingthe series of processes described above and with reference to FIG. 9.

In accordance with the disclosed embodiments, it is possible to form theconductive interconnection patterns having smaller widths and intervalsthan the widths and intervals of the mask patterns in a photolithographyprocess.

In accordance with disclosed embodiments, it is possible to form theconductive interconnection patterns having smaller widths and intervalsthan the widths and intervals of the mask patterns formed in thephotolithography process by performing one photolithography process andone etch-back process to form a mound or sheath-like shapes.

While the present invention has been described with respect to specificembodiments, it is noted that the present invention may be achieved invarious ways by performing substitution, change, and modification, bythose skilled in the art without departing from the spirit and/or scopeof the present invention as defined by the following claims. Therefore,it should be noted that the embodiments are not intended to berestrictive, but rather descriptive.

What is claimed is:
 1. A semiconductor device, comprising: a lowerinterlayer dielectric layer; a conductive interconnection patternstructure and a filling pattern over the lower interlayer dielectriclayer; and an upper interlayer dielectric layer over the conductiveinterconnection pattern structure and the filling pattern, wherein theconductive interconnection pattern structure includes: an intermediatepattern in the center thereof; a first conductive interconnectionpattern on a first side surface of the intermediate pattern; and asecond conductive interconnection pattern on a second side surface ofthe intermediate pattern, wherein the first conductive interconnectionpattern and the second conductive interconnection pattern have asymmetrical structure to each other.
 2. The semiconductor device ofclaim 1, wherein the first conductive interconnection pattern has afirst side surface that is vertically flat and a second side surfacethat is inclined and rounded.
 3. The semiconductor device of claim 2,wherein the second side surface of the first conductive interconnectionpattern has a relatively small top horizontal width and a relativelylarge bottom horizontal width.
 4. The semiconductor device of claim 1,wherein the second conductive interconnection pattern has a first sidesurface that is vertically flat and a second side surface that isrounded.
 5. The semiconductor device of claim 4, wherein the second sidesurface of the second conductive interconnection pattern has arelatively small top horizontal width and a relatively large bottomhorizontal width.
 6. The semiconductor device of claim 1, wherein thefirst conductive interconnection pattern and the second conductiveinterconnection pattern each include a metal.
 7. The semiconductordevice of claim 1, wherein the intermediate pattern has first and secondside surfaces that are vertically flat.
 8. The semiconductor device ofclaim 1, wherein the intermediate pattern includes a dielectricmaterial.
 9. The semiconductor device of claim 1, wherein the fillingpattern has a relatively small bottom horizontal width and a relativelylarge top horizontal width.
 10. The semiconductor device of claim 9,wherein the filling pattern has negatively rounded side surfaces. 11.The semiconductor device of claim 1, wherein the filling patternincludes a dielectric material.
 12. The semiconductor device of claim 1,wherein each of the conductive interconnection pattern structure furtherincludes: a first barrier pattern disposed between the intermediatepattern and the first conductive interconnection pattern; and a secondbarrier pattern disposed between the intermediate pattern and the secondconductive interconnection pattern.
 13. The semiconductor device ofclaim 12, wherein the first barrier pattern includes a vertical portionbetween the first side surface of the intermediate pattern and the firstside surface of the first conductive interconnection pattern and ahorizontal portion between a bottom surface of the first conductiveinterconnection pattern and a top surface of the lower interlayerdielectric layer.
 14. The semiconductor device of claim 12, wherein thesecond barrier pattern includes a vertical portion between the secondside surface of the intermediate pattern and the first side surface ofthe second conductive interconnection pattern and a horizontal portionbetween a bottom surface of the second conductive interconnectionpattern and a top surface of the lower interlayer dielectric layer. 15.The semiconductor device of claim 12, wherein the first and secondbarrier patterns include titanium nitride.
 16. The semiconductor deviceof claim 12, wherein the second side surface of the first conductiveinterconnection pattern and the second side surface of the secondconductive interconnection pattern abut on both side surfaces of each ofthe filling pattern, respectively, the first side surfaces and bottomsurfaces of the first conductive interconnection pattern abut on thefirst barrier pattern, and the first side surfaces and bottom surfacesof the second conductive interconnection pattern abut on the secondbarrier pattern.
 17. The semiconductor device of claim 1, wherein thefirst and second conductive interconnection patterns and the fillingpattern are coplanar with one another.
 18. The semiconductor device ofclaim 1, further comprising a stopper layer between the lower interlayerdielectric layer and the filling pattern, wherein the stopper layerincludes a harder dielectric material than included in the lowerinterlayer dielectric layer and the filling pattern.
 19. Thesemiconductor device of claim 1, further comprising a capping layerbetween the filling pattern and the upper interlayer dielectric layer,wherein the capping layer includes a harder dielectric material thanincluded in the filling pattern and the upper interlayer dielectriclayer.
 20. The semiconductor device of claim 1, wherein an averagehorizontal width of the intermediate pattern, a maximum horizontal widthof the conductive interconnection pattern structure and a minimumhorizontal width of the filling pattern are substantially equal to oneanother.
 21. A method for fabricating a semiconductor device,comprising: forming a stopper layer; forming an intermediate patternmaterial layer over the stopper layer; forming a plurality of firstpreliminary intermediate patterns by patterning the intermediate patternmaterial layer; forming a plurality of second preliminary intermediatepatterns by shrinking the first preliminary intermediate patterns;forming a conductive material layer to cover the second preliminaryintermediate patterns; forming a plurality of preliminary conductiveinterconnection patterns by patterning the conductive material layer;forming a filling layer between the preliminary conductiveinterconnection patterns; and forming a plurality of intermediatepatterns, a plurality of conductive interconnection patterns and aplurality of filling patterns by removing top portions of the fillinglayer, the preliminary conductive interconnection patterns and thesecond preliminary intermediate patterns.
 22. The method of claim 21,wherein vertical heights and horizontal widths of the first preliminaryintermediate patterns are greater than vertical heights and horizontalwidths of the second preliminary intermediate patterns.
 23. The methodof claim 21, wherein the conductive interconnection patterns includeleft conductive interconnection patterns formed on the left of theintermediate patterns and right conductive interconnection patternsformed on the right of the intermediate patterns, wherein each of theleft conductive interconnection patterns includes a flat right sidesurface and a rounded left side surface, and each of the rightconductive interconnection patterns includes a flat left side surfaceand a rounded right side surface.
 24. The method of claim 23, whereineach of the intermediate patterns includes both flat side surfaces, andeach of the filling patterns includes both side surfaces that arerounded to have negative slopes where a bottom portion is narrow and atop portion is wide.
 25. The method of claim 23, wherein the sum of ahorizontal width of each left conductive interconnection pattern and ahorizontal width of each intermediate pattern is equal to a horizontalwidth of each first preliminary intermediate pattern.
 26. The method ofclaim 23, wherein the sum of a horizontal width of each right conductiveinterconnection pattern and a horizontal width of each intermediatepattern is equal to a horizontal width of each first preliminaryintermediate pattern.
 27. The method of claim 23, wherein the sum of ahorizontal width of each left conductive interconnection pattern and ahorizontal width of each right conductive interconnection pattern isequal to a horizontal width of each first preliminary intermediatepattern.
 28. The method of claim 21, wherein the intermediate patternmaterial layer and the filling layer include at least one of siliconoxide, silicon nitride, or silicon oxynitride, or any combinationthereof.
 29. The method of claim 21, wherein the conductive materiallayer includes a metal.
 30. The method of claim 21, wherein the formingof the preliminary conductive interconnection patterns by patterning theconductive material layer includes performing an etch-back process, andthe plurality of preliminary conductive interconnection patterns areformed by separating the conductive material layer.
 31. The method ofclaim 21, wherein the removing of a top portion of the filling layer,the preliminary conductive interconnection patterns and the secondpreliminary intermediate patterns includes performing a ChemicalMechanical Polishing (CMP) process, and wherein a top surface of each ofthe intermediate patterns, the conductive interconnection patterns andthe filling patterns are coplanar with one another.
 32. The method ofclaim 21, further comprising: forming a barrier material layer betweenthe second preliminary intermediate patterns and the conductive materiallayer; and forming a plurality of barrier patterns which are physicallyseparate, by patterning the barrier material layer after the forming ofthe preliminary conductive interconnection patterns.
 33. A method forfabricating a semiconductor device, comprising: forming a lowerinterlayer dielectric layer over a substrate; forming a stopper layerover the lower interlayer dielectric layer; forming first preliminaryintermediate patterns over the stopper layer; forming second preliminaryintermediate patterns by shrinking the first preliminary intermediatepatterns; forming preliminary conductive interconnection patterns tocover top surfaces and both side surfaces of the second preliminaryintermediate patterns; forming a filling layer between the preliminaryconductive interconnection patterns; forming intermediate patterns withside surfaces, conductive interconnection patterns on the side surfacesof the intermediate patterns and filling patterns between the conductiveinterconnection patterns by removing a top portion of each of thefilling layer, the preliminary conductive interconnection patterns andthe second preliminary intermediate patterns; forming a capping layerover the intermediate patterns, the conductive interconnection patternsand the filling patterns; and forming an upper interlayer dielectriclayer over the capping layer.
 34. The method of claim 33, wherein theforming of the second preliminary intermediate patterns includespartially removing portions from the top and both sides of the firstpreliminary intermediate patterns by performing an isotropic etchprocess on the first preliminary intermediate patterns.
 35. The methodof claim 33, wherein the forming of the preliminary conductiveinterconnection patterns includes: forming a conductive material layerover the stopper layer to cover top surfaces and side surfaces of thesecond preliminary intermediate patterns; and separating the conductivematerial layer into the preliminary conductive interconnection patternsby performing an etch-back process.
 36. The method of claim 33, whereintop surfaces of the intermediate patterns, the conductiveinterconnection patterns, and the filling patterns are coplanar with oneanother.
 37. The method of claim 33, wherein the conductiveinterconnection patterns include left conductive interconnectionpatterns formed on the left of the intermediate patterns and rightconductive interconnection patterns formed on the right of theintermediate patterns, wherein each of the left conductiveinterconnection patterns includes a flat right side surface and arounded left side surface, and each of the right conductiveinterconnection patterns includes a flat left side surface and a roundedright side surface.
 38. The method of claim 37, wherein each of theintermediate patterns includes both flat side surfaces, and each of thefilling patterns includes both side surfaces that are rounded to havenegative slopes where a bottom portion is narrow and a top portion iswide.
 39. The method of claim 37, the sum of horizontal width of eachleft conductive interconnection pattern and horizontal width of eachintermediate pattern is equal to a horizontal width of each firstpreliminary intermediate pattern.
 40. The method of claim 37, whereinthe sum of horizontal width of each right conductive interconnectionpattern and horizontal width of each intermediate pattern is equal to ahorizontal width of each first preliminary intermediate pattern.